1. Field of the invention
The present invention relates generally to a method of refreshing a semiconductor memory device, and more particularly to applying a bank-based Partial Array Self Refresh (PASR) scheme to the semiconductor memory device having a piled refresh function.
2. Description of the Prior Art
As generally known in the art, the volatile memory devices such as a dynamic random access memory (DRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), and others (hereinafter the “memory devices”) require periodic refresh operations to prevent data loss in the memory cells.
The refresh operations performed in the memory devices are classified largely into two modes: the auto-refresh mode and the self-refresh mode.
In case of the auto-refresh mode, refresh operations are performed in a memory device, while the memory device is in an operating state for data access, in response to a refresh command from an external device external. In case of the self-refresh mode, refresh operations are performed in the memory device, while the memory device is in an idle state, e.g., not operating for data access, in response to a refresh command generated by the memory device itself.
A typical refresh operation consumes a large amount of electric current. The Partial Array Self Refresh (PASR) scheme has been developed to reduce the current consumption required for refresh operations performed during a self-refresh mode.
According to the PASR scheme, a refresh command is applied to the memory device in the self-refresh mode to refresh only pre-selected areas of memory cells storing data. Thus, the PASR scheme is effective only in the case when the information about the data stored in the relevant cells of the memory device is known to an external system before refreshing.
FIG. 1 illustrates a bank-based PASR scheme in a memory cell array having four memory banks: bank <0> 100, bank <1> 101, bank <2> 102, and bank <3> 103. FIG. 1 also shows a table listing the PASR codes A2, A1 and A0 according to which all or a selected number of banks are to be refreshed. Thus, the “bank-based” PASR scheme refers to a refreshing scheme for refreshing all or a sub-combination of banks 100, 101, 102, 103 according to the PASR codes A2, A1, A0 of the table in FIG. 1. For example, as shown in FIG. 1, the address signals A2, A1, A0 may be set to “0 0 1” to refresh the banks 100 and 101 but not the banks 102 and 103. When the address signals A2, A1, A0 are set to ‘0 0 0’, all memory banks 100, 101, 102, 103 are to be refreshed. When the address signals A2, A1, A0 are set to ‘0 1 0’, only the memory bank 100 is to be refreshed.
Therefore, the PASR scheme makes it possible to selectively refresh all or a certain number of specific banks, and this allows reduction of the current consumed by the memory device.
FIG. 2 is shown to illustrate the piled refresh scheme in a DDR SDRAM.
The piled refresh scheme is designed to prevent peak current consumption that may occur if all the banks 100, 101, 102, 103 are allowed to be refreshed simultaneously. Under the piled refresh scheme, the refresh operations are instead performed in sequence one bank at a given time.
For example while referring to FIG. 2, after a refresh command for the bank <0> 100 is applied, a predetermined period of time passes, and then a refresh command for the bank <1> 101 is applied. In the same manner, the bank <2> 102 and the bank <3> 103 are sequentially refreshed one by one after a predetermined time interval.
As described above, since the banks 100, 101, 102, 103 are sequentially refreshed by the piled refresh scheme, it is possible to prevent the peak current consumption which could occur if all four banks are refreshed simultaneously.
As generally known in the art, the piled refresh scheme of FIG. 2 is utilized in a DDR SDRAM in order to reduce the peak current consumption. However, the Joint Electron Device Engineering Council (JEDEC) is considering to adopt the PASR scheme, as described in FIG. 1, in the design of the next generation DDR SDRAM.
For this reason, the novel techniques of applying the PASR scheme to a DDR SDRAM utilzing the piled refresh scheme, among others, are claimed and fully described in the present application.